On-Chip Networks

Synthesis Lectures on Computer Architecture

Abstract

With the ability to integrate a large number of cores on a single chip, research into on-chip networks to facilitate communication becomes increasingly important. On-chip networks seek to provide a scalable and high-bandwidth communication substrate for multi-core and many-core architectures. High bandwidth and low latency within the on-chip network must be achieved while fitting within tight area and power budgets. In this lecture, we examine various fundamental aspects of on-chip network design and provide the reader with an overview of the current state-of-the-art research in this field.

Table of Contents: Introduction / Interface with System Architecture / Topology / Routing / Flow Control / Router Microarchitecture / Conclusions

Reviews

"A comprehensive discourse on on-chip networks... The authors are successful in meeting the demand for this broad community of readers [and] motivated to discuss topics ranging from basic concepts in on-chip networks to state-of-the-art design issues. These objectives are nicely met, and thus the book can be used as a jump-start for newcomers to the OCN area." Log into Computing Reviews to read the full review, http://www.reviews.com.